1. Field of the Invention
The present invention relates to circuitry for applying reading, programming and erasing voltages to wordlines of EEPROM arrays (including flash EEPROM arrays) and to the control gates of the individual memory cells attached to those word lines while reducing the latch-up phenomenon that can occur during high/low voltage switching operations. More specifically, the present invention relates to isolation circuitry for controlling the discharge of high-voltage in an EEPROM.
2. Description of the Related Art
EEPROM arrays typically require circuitry that will switch as many as four different values of voltage to each wordline for the purposes of reading, programming and erasing information stored on the floating gates.
For example, as shown in FIG. 1, during a read operation of EEPROM cells of the floating gate type, shown and described in U.S. Pat. No. 5,572,054, whose disclosure is incorporated herein by reference, the common source line 14 of the array 500 is brought to a ground potential. The selected column address line 18a, supplied to the selected memory cell 100, is brought to +2 volts. The selected row address line 62a, connected to the selected memory cell 100, is brought to +5 volts. The selected memory cell 100 can then be read out.
During programming of such EEPROMs, the column address line 18a is brought to ground potential or a low potential between, for example, ground and +1 volt. The particular row address line 62a, which is connected to the gate 28 of the particular memory cell 100 to be programmed is brought to +1 volt or higher depending upon the voltage of the column address line 18a. The unselected row address lines 62(b . . . z) are brought to a ground potential. The common source line 14 of the memory array 500 is brought to a high positive potential, such as +12 volts. The unselected column lines 18(b . . . z) are brought to a high potential, such as +5 volts. This causes programming of the selected memory cell 100.
Finally, during erasing operations of these EEPROMS, the plurality of column address lines 18(a . . . z) are all brought to a ground potential. The plurality of row address lines 62(a . . . z) are all brought to a high positive potential, such as +15 volts. In this manner, all of the memory cells 100 in the memory array 500 are erased.
When only a selected row of the memory array 500 is to be erased, the particular row address line, e.g., 62a, is raised to a high positive potential, such as +15 volts with the rest of the row addresses at ground potential. In this manner, only the memory cells in row 62a are erased.
The various EEPROM wordline voltages may be generated from the external power supply V.sub.DD using charge-pump capacitors located on the memory chip. Circuits for switching from one voltage to a second voltage are well known. However, in the case of EEPROMs, there is a need for improved circuits that will switch wordline reading and programming voltages. Switching of voltages presents a unique problem in that such circuits must be designed to prevent P/N junctions between the diffused areas and the substrate of such integrated circuits from becoming forward biased during application of switched voltages.
Furthermore, the voltage levels of internal nodes of a memory system are influenced by the capacitances of such nodes and by other intrinsic parasitic effects. As a result, the changing potentials on such nodes during transitions between application of read voltages and the much higher programming/erasing voltages may undesirably forward bias P/N junctions within the memory system.
The forward biasing of such P/N junctions may in turn lead to undesirable latch-up conditions. Accordingly, it is necessary to control such voltage transitions occurring between read and program or erase operations in a manner that prevents the undesirable forward biasing of P/N junctions within the memory system.
A conventional solution to the latch-up problem is disclosed in U.S. Pat. No. 5,774,406. As shown in FIG. 2, the latch-up problem may be alleviated by providing an NMOS transistor 1 having a large channel width-to-length (W/L) ratio between program line Vpp and the supply voltage VDD of memory system 10.
Although effective in preventing latch-up conditions, the inclusion of transistor 1 within memory system 10 may be problematic. For example, during the operations of memory system 10 in which oscillator 2 and charge pump 3 are inactive (during read operation), transistor 1 pulls line V.sub.pp to a maximum voltage equal to the supply voltage V.sub.DD less the threshold voltage V.sub.th of transistor 1. As a result, the voltage levels of nodes within memory array 4 and any additional associated logic circuitry that is designed to operate from the supply voltage V.sub.DD will in practice be limited to less than a full rail-to-rail voltage swing.
That is, the supply voltage is effectively reduced to V.sub.DD -V.sub.th. Since the threshold voltage of a typical NMOS transistor is typically 1V, this reduction in the effective supply voltage V.sub.DD becomes significant for low-voltage operations. For example, when the supply voltage V.sub.DD is 2.7V, the inclusion of transistor 1 in memory system 10 forces memory array 4 to operate within approximately a 1.7V voltage swing, thereby rendering an efficient operation of memory system 10 unpractical.
Moreover, memory system 10 suffers from another serious drawback. At the end of a programming cycle, additional circuitry (not shown) is required to discharge line V.sub.PP from a high program voltage to a lower read voltage (typically V.sub.DD or lower). This additional circuitry, in addition to consuming valuable silicon real estate, undesirably draws DC current from the supply voltage V.sub.pp thereby wasting power.